1. Field of the Invention
The present invention relates to the field of emulation systems. More specifically, the present invention relates to methodology for increasing capacity of an emulation system.
2. Background Information
Emulation systems for emulating circuit designs are known in the art. Typically, prior art emulation systems are formed using conventional general purpose field programmable gate arrays (FPGAs) and general purpose routing chips. A circuit design to be emulated is “realized” on the emulation system by compiling a “formal” description of the circuit design, and mapping the circuit design onto the logic elements (LEs) of the FPGAs and the routing chips.
As circuit designs have become larger and larger, up to and including designs having millions of transistors, a similar increase in size of emulation systems has become necessary in order to emulate such circuit designs. Large emulation systems typically include a significant number of FPGAs as well as a significant number of routing chips to route signals between the FPGAs. However, given the large number of FPGAs which may be included in an emulation system, the number of routing chips required to provide adequate flexibility to concurrently route large numbers of input and output signals to and from an FPGA has become prohibitively expensive.
An article by Jonathan Babb et al. entitled “Logic Emulation with Virtual Wires”. (hereinafter “Babb et al.”) provides one solution to this problem, referred to as “time multiplexing” or the use of “virtual wires”. Using time multiplexing, multiple logical outputs of an FPGA share a single physical output with only one of the logical outputs being able to output a signal on the single physical output in any given clock cycle. Thus, the logical outputs are multiplexed on the single physical output over time. Similarly, a physical input to an FPGA is shared by multiple logical inputs with only one of the logical inputs being able to receive an input signal on the physical input in any given clock cycle. All of the FPGAs in the Babb et al. system, as well as any routing chips interconnecting the FPGAs, are clocked by the same clock signal (see, Babb et al., p. 5, § 2.1).
One problem with the Babb et al. system is that it is primarily designed to emulate synchronous logic providing synchronous signals, and does not support time multiplexing of asynchronous signals for emulating asynchronous logic. Rather, such asynchronous signals must be hard-wired to dedicated FPGA physical inputs and outputs, while the interconnection of time multiplexed synchronous signals is automatically configured for the user (see, Babb et al., p. 5, § 2.1).
Additionally, even with the use of time multiplexing, or in systems where asynchronous signals are hard-wired to dedicated inputs and outputs, other problems still exist. One such problem is that of synchronizing clock signals in the emulation system. Despite the use of time multiplexing to reduce overall system size, the system can still remain relatively large. Such systems can range in size up to a few meters square. Synchronizing high frequency clock signals across such a large area creates a significant problem.
Thus, it is desirable to have an emulation system with improved capacity without the disadvantages of conventional time multiplexing. As will be described in more detail below, the present invention provides for an emulation system that achieves these and other desired results, which will be apparent to those skilled in the art from the description to follow.